Moore’s law scaling dead by 2021, to be replaced by 3D integration

Over the past few years, we’ve chronicled the transformation of Moore’s Law. Originally coined as a way to explain ongoing improvements in transistor scaling, Moore’s law has been redefined and extended to include long-term trends in semiconductor performance and the integration of new chip features. Now, the International Technology Roadmap for Semiconductors (ITRS) has released a new update on the future of semiconductor technology that states conventional 2D transistor density scaling will likely end by 2021 — to be replaced by new and different types of integration and scaling.

Much of the ITRS’ recently released executive report focuses on the way the meaning of Moore’s law has changed over the years. We discussed this back in 2015 when we noted the need for a Moore’s law 3.0, as the focus of the semiconductor industry shifted from shrinking individual chips to an SoC or device-centric model, which emphasized capability integration and power consumption reductions. The modern cell phone is an example of this third type of integration, which combines a high-definition screen, high-speed cellular and wireless network, a touchscreen interface, high-quality cameras capable of capturing both photos and video, a short-range flashlight (thanks to an integrated flash), and 16-128GB of internal storage. All of this capability is combined with a high-speed system-on-chip that operates well above 1GHz.

The benefits of 3D stacking.

The shift from 2D to 3D structures is going to be much simpler for some technologies than others. One of the major challenges of adopting 3D construction for logic circuits, like CPUs, is that stacking memory transistors on top of logic transistors could melt one or both layers if too much heat is trapped within the die. We’ve already seen NAND flash make the shift to 3D manufacturing, but 3D CPUs aren’t expected until the 2021 – 2024 timeframe. Between now and then, manufacturers are expected to integrate other materials, like silicon-germanium (SiGe) or III-V semiconductors (semiconductors from groups III and V of the periodic table) to improve on current performance.



One point the ITRS reiterated that we’ve also covered before at ET is that the nature of what constitutes advancement and how we characterize that performance improvement will continue to emphasize low power over strict clock advances. This is partly due to the nature of what the market is demanding, and partly due to the limited ability of current materials to hit higher clock rates. As the graph above shows, only van der Waal FETs are expected to even match high-power CMOS in terms of absolute performance, albeit at significantly reduced power consumption. In thermally constrained environments, the vdWFETs and exFETs are significantly faster when constrained to a power envelope of 10W/cm².

One alternative floated by the ITRS is that we may see improvements in the usage of highly specialized heterogeneous cores that utilize either unique function blocks or are highly tuned to particular applications. This has been a proposed solution to the so-called dark silicon problem that we’ve covered before, and it’s relatively easy to explain. Instead of building multi-core blocks with an increasing number of similar chips, manufacturers would use some of that space to build processors dedicated to specific tasks. Conceptually, this would mean that your camera might have one dedicated processor, while other applications could run on other cores. Some research projects have explored building small cores to handle tasks at an application level, but the ITRS report doesn’t delve into this detail.

Here’s how NAND and DRAM compare across a variety of metrics. Image included mostly for being interesting.

One point that the ITRS report makes, but doesn’t necessarily come right out and say, is that we’re going to see this kind of integration and envelope-pushing in the heart of IoT development before it comes to desktops, laptops, and the like. The reason is simple, and as inferred above: Right now, the silicon industry is pushing hard to create chips that can run on less and less power while simultaneously improving power consumption. If you want to build a next-generation wearable, cutting power consumption from 1W to 0.75W is a huge improvement. But the technologies that allow you to cut that 0.25W of power may not translate well to devices in the 15W-140W laptop and desktop range. Similarly, building 3D chips with integrated CPUs requires appropriate thermal dissipation, which means the first chips to rely on these methods will probably be extremely low-power devices — not the kind of cores in your laptop or desktop.

In fact, it’s somewhat telling that while the ITRS’ executive summary makes extensive predictions regarding future device frequencies, bandwidths, and operating characteristics at the data center, mobile, and Internet of Everything (the proposed successor to the Internet of Things), it does not attempt to predict the future of conventional desktops and laptops. The closest it comes is predicting that by 2029 the average mobile processor will contain 25 application processors and 303 GPU cores, with a max single-component frequency of 4.7GHz (presumably burst frequency).

The implications of the report are clear: Those who seek significantly improved CPU performance will do best to seek it via new computing architectures, improved multi-threading, or improved memory performance in general — not via improvements to raw clock speed. With Intel stuck in the doldrums when it comes to providing architectural improvements, we wouldn’t hold our breath on this front.